About

I am currently doing job as a software Engineer with 8 months experience . B.Tech Pass out from chitkara University, Punjab with 8.6 CGPA ( B.Tech Computer science Engineering)

Role

Alma Mater:

B.E. in Compter Science and Engineering
Chitkara inSTITUTE OF THECHNOLOGY
2012 to 2016

Experience:

software engineer
Infosys Pvt Limited
2016 to 2017
Babytud
Answer
1 year 1 month ago

Hi @sumit please tell me how to reduce solution?

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Babytud
Answer
1 year 1 month ago
I guess images are still not visible properly so i have attached the link of question
Problem is that i am able to solve question and able to get correct answer by multiplying all diagonal elements but for making upper triangular matrix zero solution is too big.could you please solve that or tell me how to reduce it
moreless
rbrgate's picture
Ravindra Babu Ravula
virtualgate's picture
Virtual GATE
pritam's picture
Pritam Prasun
pritam's picture
Pritam Prasun
905

Hi @sumit please tell me how to reduce solution?

more less
I guess images are still not visible properly so i have attached the link of question
Problem is that i am able to solve question and able to get correct answer by multiplying all diagonal elements but for making upper triangular matrix zero solution is too big.could you please solve that or tell me how to reduce it
more less

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns. 

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Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns. 

more less